This comprehensive Static Timing Analysis (STA) course is designed to take participants from fundamental concepts to industry-level expertise in timing verification and analysis. The course covers the complete spectrum of STA, including timing constraints, setup and hold analysis, clock domain crossing, multi-mode multi-corner analysis, and advanced optimization techniques used in modern VLSI design.

Participants will gain hands-on experience with industry-standard STA tools and learn to apply timing closure methodologies used in real-world chip design projects. The course combines theoretical foundations with practical applications, enabling engineers to perform timing analysis, debug timing violations, and implement effective timing closure strategies.

By the end of this course, participants will be proficient in analyzing complex timing paths, understanding timing reports, applying timing constraints correctly, and resolving timing issues in both digital and mixed-signal designs. The curriculum emphasizes real-world scenarios and best practices followed in leading semiconductor companies.

Module 1: Introduction to Static Timing Analysis

Duration: 6-8 hours

1.1 Fundamentals of Timing

What is Static Timing Analysis and why it's needed

Comparison: STA vs Dynamic Simulation

STA in the ASIC design flow

Key terminology and concepts

1.2 Timing Paths and Components

Understanding timing paths: data paths and clock paths

Launch and capture concepts

Path groups and classifications

Timing arcs in standard cells

1.3 Delay Calculation Basics

Cell delay and propagation delay

Net delay and interconnect delay

Transition time and slew

Capacitance and its impact on delay

Module 2: Setup and Hold Timing Analysis

Duration: 8-10 hours

2.1 Setup Time Analysis

Setup time requirement and violations

Setup timing equation and calculations

Data arrival time and data required time

Setup slack computation

2.2 Hold Time Analysis

Hold time requirement and violations

Hold timing equation and calculations

Hold slack computation

Relationship between setup and hold

2.3 Timing Violations and Recovery

Identifying setup and hold violations

Common causes of timing failures

Basic timing optimization techniques

Buffer insertion and gate sizing

2.4 Practical Exercises

Analyzing simple timing paths

Manual timing calculations

Using STA tools for basic analysis

Debugging timing violations

Module 3: Clock Tree and Clock Domain Analysis

Duration: 10-12 hours

3.1 Clock Characteristics

Clock definitions and properties

Clock latency: source and network

Clock uncertainty: skew and jitter

Clock transition requirements

3.2 Clock Tree Synthesis Concepts

Clock tree structure and topology

Clock skew and its impact on timing

Useful skew concepts

Clock tree optimization strategies

3.3 Generated and Virtual Clocks

Generated clock definitions and applications

Virtual clocks for I/O timing

Clock relationships and interactions

Multi-frequency clock designs

3.4 Clock Domain Crossing (CDC)

Synchronous vs asynchronous clock domains

CDC timing challenges

Safe CDC structures: synchronizers

False paths and multicycle paths in CDC

3.5 Hands-On Labs

Clock tree analysis in real designs

Defining clock constraints

Analyzing clock skew reports

CDC analysis and verification

Module 4: Timing Constraints and SDC

Duration: 10-12 hours

4.1 Introduction to SDC Format

Synopsys Design Constraints overview

SDC file structure and syntax

Common SDC commands

Constraint priorities and overrides

4.2 Clock Constraints

create_clock command and options

create_generated_clock for derived clocks

set_clock_latency and set_clock_uncertainty

set_clock_transition and other clock properties

4.3 I/O Constraints

Input and output delay constraints

set_input_delay and set_output_delay

Modeling external environments

Virtual clocks for I/O timing

4.4 Path-Specific Constraints

set_false_path for non-timing critical paths

set_multicycle_path for relaxed timing

set_max_delay and set_min_delay

Case analysis and disable timing

4.5 Design Rule Constraints

set_max_transition constraints

set_max_capacitance constraints

set_max_fanout constraints

Load and drive strength specifications

4.6 Constraint Development Workshop

Writing complete SDC files

Constraint validation techniques

Common constraint mistakes

Best practices for constraint management

Module 5: Advanced Timing Concepts

Duration: 12-14 hours

5.1 On-Chip Variation (OCV) Analysis

Process, voltage, and temperature (PVT) variations

OCV derating factors

Path-based OCV vs graph-based OCV

OCV impact on setup and hold timing

5.2 Advanced OCV Methodologies

Advanced On-Chip Variation (AOCV)

Parametric On-Chip Variation (POCV)

Statistical Static Timing Analysis (SSTA)

Comparison of OCV, AOCV, and POCV

5.3 Multi-Mode Multi-Corner Analysis

Understanding process corners

Voltage and temperature corners

Operating modes and scenarios

MCMM analysis setup and execution

5.4 Timing Exceptions Deep Dive

Complex false path scenarios

Advanced multicycle path applications

Path-specific timing exceptions

Exception conflict resolution

5.5 Special Timing Scenarios

Latch-based timing analysis

Combinational loops and their handling

Three-state and bidirectional timing

Asynchronous reset timing

Module 6: Timing Reports and Analysis

Duration: 8-10 hours

6.1 Understanding Timing Reports

Timing report structure and sections

Path delay breakdown analysis

Slack calculation verification

Critical path identification

6.2 Report Analysis Techniques

Endpoint reports and path groups

Analyzing setup and hold reports

Transition and capacitance violations

Clock skew and latency reports

6.3 Advanced Reporting

Timing histogram analysis

Report exceptions and constraints

QoR (Quality of Results) metrics

Custom reporting and filtering

6.4 Debugging Methodology

Systematic approach to timing closure

Prioritizing timing violations

Root cause analysis techniques

Correlation between tools

Module 7: Signal Integrity and Crosstalk

Duration: 8-10 hours

7.1 Signal Integrity Fundamentals

Crosstalk mechanisms in deep submicron

Aggressor and victim nets

Coupling capacitance effects

Miller factor and coupling coefficient

7.2 Crosstalk-Induced Timing Impact

Crosstalk delay impact (delta delay)

Crosstalk-induced glitches

SI-aware timing analysis

Noise margins and thresholds

7.3 SI Analysis and Mitigation

Crosstalk analysis methodology

Shield insertion techniques

Wire spacing and sizing strategies

Crosstalk prevention guidelines

Module 8: Low Power Timing Analysis

Duration: 6-8 hours

8.1 Power-Aware Design Concepts

Unified Power Format (UPF) overview

Power domains and power states

Voltage islands and level shifters

Retention and isolation cells

8.2 Timing Analysis with Power Modes

Multi-voltage timing analysis

Level shifter timing considerations

Power mode setup and hold analysis

State retention timing

8.3 Dynamic Voltage and Frequency Scaling

DVFS timing challenges

Voltage-dependent delays

Timing closure across power modes

Module 9: Industry Tools and Flows

Duration: 10-12 hours

9.1 Industry-Standard STA Tools

Synopsys PrimeTime overview

Cadence Tempus overview

Tool comparison and selection criteria

License management and optimization

9.2 Tool-Specific Features

PrimeTime advanced features and commands

Tempus parallel processing capabilities

ECO generation and implementation

What-if analysis and scenarios

9.3 Integration with Design Flow

Synthesis to STA handoff

Place and route integration

Sign-off timing verification

GDS to timing correlation

9.4 Hands-On Tool Sessions

Setting up timing analysis environment

Running complete timing analysis

Generating comprehensive reports

ECO implementation and verification

Module 10: Timing Closure Strategies

Duration: 10-12 hours

10.1 Timing Closure Methodology

Hierarchical vs flat timing closure

Top-down and bottom-up approaches

Iterative optimization flow

Convergence criteria and goals

10.2 Optimization Techniques

Logic restructuring for timing

Gate sizing and Vt swapping

Buffer insertion strategies

Useful skew optimization

10.3 Physical Optimization

Placement optimization for timing

Routing detour and layer assignment

Clock tree optimization

Hold fixing strategies

10.4 Sign-Off Timing Closure

Sign-off checklist and requirements

Final timing verification

ECO freeze and tape-out criteria

Post-silicon timing correlation

10.5 Real-World Case Studies

Timing closure on complex SoC designs

Handling million-instance designs

Meeting aggressive timing targets

Lessons learned from production designs

Module 11: Advanced Topics and Best Practices

Duration: 6-8 hours

11.1 High-Performance Design Techniques

Pipeline optimization

Retiming for performance

Clock gating timing considerations

High-speed interface timing

11.2 Timing for Different Applications

High-performance computing designs

Mobile and low-power SoCs

Automotive reliability requirements

Memory interface timing

11.3 Industry Best Practices

Constraint development guidelines

Design partitioning for timing

IP integration timing considerations

Version control and reproducibility

11.4 Emerging Trends

Machine learning in timing closure

FinFET and advanced node considerations

3D IC timing challenges

Timing in heterogeneous integration

Module 12: Capstone Project and Assessment

Duration: 8-10 hours

12.1 Comprehensive Project

Working on a complete design

Developing full constraint set

Performing complete timing analysis

Achieving timing closure

12.2 Peer Review and Presentations

Project presentations

Design review sessions

Knowledge sharing

12.3 Final Assessment

Written examination

Practical tool-based assessment

Interview-style technical discussion

Certification criteria

Trainer Details:

Puneet Mittal – 17+ Years of Industry Experience & 5+ Years of Entrepreneur Experience. He is the Founder and CEO of VLSI Expert Pvt. Ltd.
LinkedIn Profile - https://www.linkedin.com/in/mittalpuneet

Kavita Mehta - 10+ Years of Academic experience. She is the Manager, of eLearning, and Training at VLSI Expert Pvt. Ltd. Linkedin Profile - https://www.linkedin.com/in/kavita-mehta-094035b/ 

Industry Expert 1 (As a Subject Matter Expert) – 10+ years of Industry Experience and expertise in Circuit design. IIT Ropar alumni & Ph.D. from IITD

Industry Expert 2 (As a Visiting Faculty) – 5+ years of Industry Experience & Expertise in Design Automation and verification.

Industry Expert 3 (As a Subject Matter Expert) - 8+ years of Industry Experience & Expertise in Memory Circuit & Layout Design. BITS Pilani Alumni - Highest Education M.Tech

Industry Expert 4 (As a Subject Matter Expert) - 9+ years of Industry Experience & Expertise in Physical Design - IIT Ropar alumni & Ph.D. from the USA 

Industry Expert 5 (As a Subject Matter Expert) - 9+ years of Industry Experience & Expertise in Physical Design - BITS Pilani Alumni - Highest Education M.Tech