VLSI EXPERT PVT. LTD. ensures that we give you the stairs so that you can reach the summit of success. Our Physical Design course is one of the TOP Rated courses and is highly recommendable by Industry Professionals.  Our Physical Design course has been designed around Synopsys Tool and we provide Individual Tool Access 24*7 throughout the training program. 

We guarantee you that once you decide to take this exhilarating journey of RTL to GDS flow using Synopsys Tool Environment with us you will feel joy of coming closer of being an expert in the domain each day. The course is designed keeping in view the Industry Standard Practices by the industry experts themselves.

This course will help the attendees to understand and gain proficiency in STA, Logic Synthesis, Place and Route from a Low Power Design Perspective.

Tools Used:
Lab session on Industry Tools By Synopsys

DC-DESIGN COMPILER (Synthesis Tool)

ICC2-IC COMPILER 2(Physical Design Tool, Netlist to GDS II Implementation)

PT-PRIME TIME (Timing Sign-Off tool)

Goal Of VLSI EXPERT PRIVATE LMITED

We would target a capability of training up to 3000 faculty/students/industry representatives per year.

Providing a platform to faculty members/students/industry representatives/researchers for their professional growth.

Generate manpower in the Semiconductor Domain and make everyone industry-ready. 

Contribute to the growth of country by developing skills to create better opportunities for employability.

Module 1: VLSI Flow Introduction:

VLSI Implementation Flow Overview

Basic Idea of all stages and Terminology Introduction

Input Output Files

Mapping files, GDS layer, Technology Files, Techlib concepts, 

Nxtgrd files, Tluplus files, DRC Rules, Routing rules, models files, LVS rules

Libraries in Physical Design 

Physical library, Technology file library 

Cell Libraries Standard cell library, I/O cell library, Custom/Macro cell library

Overview of Hierarchical Design Vs Flat Design

Concepts of Blocks, Top level design

Tradeoff b/w Flat Vs Hier. design (Timing perspective)

Module 2: Unix, Scripting & pre-requisite

Unix Basic commands, Scripting Concepts (TCL basics)

CMOS Concepts Introduction

Assignment – TCL, Unix and CMOS

Module 3: Logic Synthesis (Conceptual Class):

Introduction and Importance of Synthesis in ASIC Design

Synthesis Design Timing Constraints

Design Rule Constraints (DRC) - Maximum Transition time, Maximum Fanout, Max & Min Capacitance

Optimization Constraints -Input and Output Delays, Minimum and Maximum Delay,  Maximum Area, Power Optimization.

Managing Constraints Priorities

Overview of SDC constraints

Timing Concepts and Optimization Techniques

Path based Timing Optimizations

Path grouping, Ungrouping, boundary opt., register retiming, seq inversion

Architectural, Logical and Gate-Level Optimization

Assignments - Synthesis Opt, Basic Synthesis

Module 4: Design compiler (Lab):

Conceptual Classes:

Synthesis Tool (Design Compiler) Flow (DC & DC-T Flow)

Synthesis Runs and Analysis, Different directory structure & input files and their syntax and uses

Demo of Synthesis Scripts & Different Synthesis Reports

Overview of Different commands used by DC & Linking of these commands with the concepts

Sequence of different files needed by DC

• Reporting structure
• Understanding of different output formats and output files 

Assignments around Synthesis DC Flow Setup

LAB Work

ICC2 Tools Basic Setup and Introduction

MCMM File in ICCII, PVT

Different directory structure, 

Linking of different files or wrappers and scripts 

ICC GUI or Batch Mode

Different input files

Reporting structure

Link library, Target library, 

Module 5: Floorplan & Power Planning

Conceptual Classes

Pre-Floorplan Sanity Checks

Power Domains, Power Planning and Layer Planning

PPNS in ICCII

Macros concepts, Guideline to place Macros

DEF / LEF concepts

Core / Die concepts, IO-pad concepts

Site rows, Grid, Tracks concepts

Power Ring, Pad Ring, Vertical & Horizontal Strap

Lab Work

Introduction of ICC commands & uses to set FP guideline

GUI understanding

Module 6: Placement

Conceptual Classes

Pre-placement Sanity Check

Standard cell Concepts

Global Placement, Refine Placement & Detailed Placement

Congestion Driven Placement

Timing Driven Placement

Power Driven Placement

Special Cell placement

Logic Optimization in Placement 

Special cells / Spare cells concepts

Blockage Concepts

Placement Congestion: cell density

Lab Work

Introduction of Different placement related commands

Module 7: CTS (Clock Tree Synthesis)

Conceptual Classes

Goals of CTS

Clock Buffers and Inverters

Skew Balancing

CTS Algorithms

Clock Tree Optimization

Pre & Post CTS Clock Tree Structure

Clock Design Problems

Module 8: Routing

Conceptual Classes

Global Routing, Track Routing, Detailed Routing

Routing Blockages

Timing driven routing

Concepts of HVH / VHV routing

Metal wire concepts (Mx/My/Mz etc)

Default rules Vs NDR rules

Module 9 – Lab Work and Project

How to do different analysis / checks (Timing analysis, DRC Checks)

Assignments based on PNR concepts

Demo on a Small test case using  commands (Manual running

Module 10: Static Timing Analysis

Conceptual Session

Delay concepts (Cell delay and Net delay)

Delay calculation Methodology (GBA and PBA analysis)

Different files – Liberty File, SDC, SDF file, Wire Load model File, SPEF Files

Timing Path and Timing Checks (Setup and Hold, Clock gating Checks, Recovery, Removal)

Analysis Mode

• Single corner mode
• BC/WC corner mode
• OCV corner analysis

Fixing of Setup and hold Violation

Advance Timing concepts -OCV (derates), AOCV, POCV, CRP, CRPR, 

Timing Constraints

• Multicycle paths, False paths
• Overview of SDC file

Signal Integrity and Cross Talk

Complex Timing Analysis 

• Latch based Timing analysis
• Multi-Corner Timing Analysis

Assignment - Timing Analysis

Lab : Primetime (LAB)

Different directory structure

Different input files and their syntax and uses

Prime Time Tool Flow understanding and Timing analysis

Sequence of different files needed by Primetime

Understanding Timing Reports

GUI based Timing analysis

Script and flow understanding

Overview of Different commands used by Primetime

Importance of those commands 

Linking of these commands with the concepts (we studied)

Demo on a Small test case using those commands (Manual running)

Overview of different concepts to run primetime scripts

How to set Link library, Target library, 

How to set different values or read a script/template while running PT (using an automated flow)

Module 11: Signoff and Other Concepts

Signoff Timing and Timing ECOs

Parasitic Extraction

Interconnect parasitic. 

Process variation.  

Manufacturing defects

Coupling and Surface cap & Resistance – SPEF File

Technology files (ITF file)

Physical Verification - DRC / LVS

DFM

Antenna fixing, Critical Area, Via Reliability, Metal fill insertion, Filler cell insertion

Module 12: Low Power

Low Power Design and Architecture

CPF / UPF Format

Basic Power related Concepts

Power domain, Clock Domain, 

Dynamic Power, Switching Power, Static Power

Different kind of cells

Retention Cells, Always-ON Cells

Power Switches, Clock Gating Cells

Assignment 

Module 13: Project Details

Project on a small block

Lab access - Synopsys (DC, ICC2, PT)

Tech Node - 32nm/28nm/14nm

Small Labs and Assignment

Project: - 1 Full project.

NOTE: This Course Content is basically for your understanding and it's not limited to this only. We are enhancing and modifying our course content batch by batch and the target audience's point of view. During the Discussion, if we have to cover anything outside (but related to the topic), we are happy to do that.

Trainer Details:

Puneet Mittal – 17+ Years of Industry Experience & 5+ Years of Entrepreneur Experience. He is the Founder and CEO of VLSI EXPERT PVT. LTD.
LinkedIn Profile - https://www.linkedin.com/in/mittalpuneet

Industry Expert 1 (As a Subject Matter Expert) – 12+ years of Industry Experience and expertise in MixSignal Physical Design. IIT Ropar alumni & Ph.D. from the USA

Industry Expert 2 (As a Visiting Faculty) – 5+ years of Industry Experience and expertise in Static Timing Analysis (especially in Signoff STA). 

Q- Who is going to give this training?

ANS: This training is being conducted by "VLSI EXPERT PVT. LTD.". We have our Trainers and Industry Experts. Please Check the Instructor Tab for more details.

Q:- What is going to be the mode of delivery of this training?

ANS: This is an Instructor-Led Online (Live) Training.

Q: - What if I miss a session?

ANS: No issues. If you miss a session the same will be available on our online platform and you can go through it as many times as possible though the instructor won’t be available to solve your queries. Access to these recordings will have lifetime (by default 10 years but you can get an extension later by contacting us).

Q: - Is it a Certification Course?

ANS: - Yes this is a certification Course. You will get the course completion certificate.

Q: - Who will give the training Certificate?

ANS: - The training Certificate will be given by " VLSI EXPERT PRIVATE LIMITED".

Q: - Can I get a refund of my fee (in case of an emergency)?

ANS: - No, this is not a refundable course. But you can request access to the next batch in case of any emergency.

Q: - Is it a Placement Oriented Program?

ANS: - No, this is not a placement-oriented program. This is a level 2 program. We can assist or refer to companies in case we get any request from companies but giving any kind of assurance for placement is not part of this program. For placement-oriented programs please check our other courses.