RTL to GDSII
Digital Design Flow (Physical Design)
Full digital design flow from RTL simulation through logic synthesis, floorplan, placement, CTS, routing, parasitic extraction and timing signoff — using Synopsys VCS, Design Compiler, IC Compiler II, StarRC and PrimeTime.
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Schematic to GDSII
Custom Design Flow (Analog Layout)
Custom IC design flow — schematic design, circuit simulation, layout design, DRC/LVS, PVT corners and standard cell design level. Using Synopsys tools for the complete analog custom flow.
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