Duration
4 Months
Assignments
21
Tools
VCS · Verdi
Seats
25
Placement
Not Oriented
ℹ️ Upskilling program — not placement-oriented. For the placement program see Foundation of VLSI Design →
Module 1
Digital Basics
FSMs, counters, combinational
Module 2
Advanced Digital
MUX design, PAL/PLA, clock gating
Module 3
Linux
Basics to advanced, TCL, AWK, SED
Module 4
C/C++ Programming
OOPs, pointers, file handling
Module 5
Verilog HDL
RTL, gate-level, IP/protocol coding
Module 6
SystemVerilog
Constrained random, coverage, SVA
Module 7
UVM
Agent, driver, monitor, sequences
Module 8
Projects
I2C, AMBA, FIFO, RISC Processor
Frequently Asked Questions
Who should take this course?
RTL Design Engineers, RTL Verification Engineers, R&D Engineers, Application Engineers, Product Validation Engineers. Also suitable for B.E./B.Tech 2nd–4th year, M.E./M.Tech 1st–2nd year and passout candidates.
Is this placement-oriented?
No. This is a Level 2 upskilling program. Profile referral support is available but placement assurance is not part of this program. See Foundation of VLSI Design for the placement-oriented program.
What tools will I get access to?
Synopsys VCS (simulation) and Verdi (debug) throughout the training with individual 24×7 access.
What if I miss a session?
Missed online sessions are recorded and available on the platform for unlimited review. Instructor queries are available only in live sessions and doubt-clearing calls.
What protocols are covered in projects?
I2C, AMBA-APB, AMBA-AHB and AMBA-AXI — the on-chip protocols used in real SoC designs. Also FIFO (synchronous and asynchronous), Dual Port RAM, Traffic Light Controller and RISC Processor.
ASIC VerificationSystemVerilog + UVM · VCS + Verdi · 4 Months · 21 Assignments · Real SoC Protocols | BatchesNoida · Mysuru · Bangalore · Online LIVE | ASIC VerificationSystemVerilog + UVM · VCS + Verdi · 4 Months · 21 Assignments · Real SoC Protocols | BatchesNoida · Mysuru · Bangalore · Online LIVE