Curriculum
What You'll Cover
- Verilog / SystemVerilog fundamentals and RTL design
- Functional simulation using VCS — compilation, elaboration, simulation
- Waveform debug using Verdi — schematic, waveform, signal trace
- Testbench architecture — components, interfaces, clocking blocks
- UVM fundamentals — factory, phases, TLM, sequences, agents
- Coverage — functional, code, toggle, FSM coverage
- Assertions — SVA, immediate vs concurrent, sequences
- Constrained random verification — randomization, constraints
- Scoreboard and checker design
- Formal verification concepts
- Industry projects — verified RTL blocks with UVM
Full details: View Full Curriculum →