ℹ️
This is an upskilling program — not placement-oriented. Designed for working professionals and graduates wanting to deepen expertise in a specific domain. For the placement-oriented program, see
Foundation of VLSI Design →Curriculum
What You'll Cover
- VLSI Backend Flow — RTL to GDSII overview
- Input/Output Files — Liberty, LEF, DEF, SPEF, SDC, TLUPlus
- Unix and Bash Scripting
- Verilog RTL Design and Simulation (VCS/Verdi)
- Static Timing Analysis — setup, hold, timing paths, slack
- Timing Constraints — clock, I/O, SDC
- Logic Synthesis — Design Compiler, technology mapping
- Floorplan — shapes, utilization, macros, keepouts
- Power Planning — rings, stripes, mesh, VDD/VSS rails
- Placement — coarse, legalize, congestion, special cells
- Clock Tree Synthesis — skew, latency, H-tree, NDR
- Routing — global, track, detailed, DRC clean
- Parasitic Extraction — StarRC, TLUPlus, SPEF
- Timing Signoff — PrimeTime, ECO, signal integrity
- Projects — full RTL to GDSII flow on real design
Full curriculum details available on the View Full Curriculum →