Module Name

Sub-Topics

VLSI Flow Introduction

(RTL to GDS)

·       RTL TO GDS Flow -VLSI Frontend Design Flow -VLSI Backend Design Flow

·       Logic Synthesis Concepts

·       Timing Optimization during Logic Synthesis

·       Floorplan Overview

·       Power Planning Overview

·       Placement Overview

·       Physical Verification Overview

·       Routing Overview

Input output Files.

(PDK Files Demystified)

·       Liberty (.lib) file

·       Power constraint, UPF file

·       Lef/Def,

·       Spice netlist,

·       Verilog netlist, Gate level netlist

·       SDC, SDF, SPEF

·       ITF file, Tech file

·       Tluplus file, Nxtgrd file

Unix and Bash Scripting

·       Basic Unix Commands

·       VI Editor

·       Bash Scripting

Verilog basic and RTL Designing

·       Basic Verilog Syntax

·       RTL design and Testbench using Verilog.

·       RTL Simulations and debugging

·       RTL level partitions

·       Hierarchical design and flat design

·       Simulation using VCS and Verdi Tool

Project

·       2 Projects in which you need to write a Verilog RTL and Simulate using VCS/Verdi

·       Same RTL we will use in further Physical Design

Static Timing Analysis

·       Delay Concepts (Cell Delay and Gate Delay)

·       Timing Paths

·       Timing Arc and .Lib File details

·       How Timing Tool do the delay calculation

·       Timing Checks (Setup and Hold; DRV)

·       Timing Reports

·       Timing Violations and Methods to Fix Violations

Timing Constraints

·       Clock Constraints

·       Input output Constraints

·       How to write Constraints for an RTL

Logic Synthesis

·       Logics Synthesis Overview

·       Technology File Overview and Mapping

·       RTL Synthesis using Design Compiler

·       Optimization techniques during Synthesis

·       Floorplan aware Synthesis

Project

·       RTL to Gate-level Netlist in different Timing Constraints using Design Compiler

·       Using the RTL during the RTL module – Map it with Technology Files in different constraint environment using Design Compiler

FloorPlan

·       Different Physical Constraints – Pin/Ports Constraints

·       Floorplan Concepts

·       Floorplan shapes (T, U, L, Rectangle, and Square) & impact of Physical Constants

·       Macros concepts, Flylines concepts

·       Hallos, Keepout margins

·       Utilization Factor, Aspect Ration

Power Plan

·       Power Stripts – VDD/ VSS Rails

·       Power Mesh

·       Power Ring

Projects

·       Floorplan and Power Plan concepts implementation using ICC2

Placement

·       Placement Blockages

·       Physical Only Cells, Spare Cells, ENDCAP Cells, TieHigh, TieLow cells, Tap Cells, Nwell Cells, DCAP Cells

·       Course Placement, Legalize Placement

·       Congestion Concepts

·       Standard Cell Concepts

CTS

·       Clock Tree Concepts

·       Concurrent Clock and Data Signal Routing

·       NDR Rules

·       Clock Skew, Clock jitter, Clock Network Delay, Clock Latency

·       H-Tree, Balance Tree , Clock Meshing

·       Effect of Clock Skew on Timing Checks

Projects

·       Placement of Synthesized Netlist using the Floorplan done in previous Module

Routing

·       Global Routing

·       Track Routing

·       Detailed Routing

·       Routing Tracks, Pitch

·        

Parasitic Extraction

·       Metal Layer Concepts

·       Foundry Tech Files

·       TluPlus Files and Nxtgrd Files

·       RC concepts and SPEF Files

Timing Signoff

·       Advance Timing Concepts

·       Fixing of Timing using ECOs

·       Signal Integrity Concept

Projects

·       Routing using the ICC2 Tools

·       Parasitic Extraction using StarRC Tools

·       Timing SignOff using the Primetime Tools

Project Review and Doubt Clearing

Placement Related Sessions

·       Mock Interview

·       Resume Preparation