INTRODUCTION TO STATIC TIMING ANALYSIS & TIMING ARC

Importance of Timing Analysis, VLSI Flow Introduction & different stages where Timing analysis happen

Different component of Timing analysis (Timing Budgeting,Timing Constraint,Timing Check,Timing Violations,Fixing of Timing Violations

Introduction about different input and output files for STA

Importance of Timing Arc & Timing Arc Representation in .LIB Files

DELAY INTRODUCTION (CELL DELAY AND NET DELAY)

Introduction of Delay Concepts

Combinational Path Delays,Sequential Path Delays

Net Delay basic (Metal Wire Concepts,Metal Stack concepts)

Gate Delay Concepts (Charging & Discharging concepts, Load related Concepts, Delay dependency on current of Inverter,Internal Capacitance,Input Capacitance and Output Capacitance concepts

DELAY MODELS & UNDERSTANDING DELAYS LIBRARIES

Gate Delay Models (How delay depends on Input Transition & Output Load,NLDM Library & CCS Library)

Net Delay Models (Transmission Line Models,Elmore Model,Wire Load Model

STA TOOL DELAY CALCULATION METHODOLOGY

Delay Calculation by STA tools (Path based Analysis and Graph Based Analysis)

Pre-Layout Delay (using wire-load model) & Post layout Delay (using SPEF File) calculation

Delay Calculation using Delay tables, Complexity across different corners.

Dependency of Delay on different parameters (PVT Corners,Manufacturing defects,RC Corners)

TIMING PATHS, TIMING EXCEPTIONS & TIMING CONSTRAINTS

Various Timing Paths (Data Path, Clock Path, Asynchronous Path,Clock Group Introduction

Representation of Timing path within Timing report

Timing Exceptions (False path, Multicycle path)

Clock Constraints,Input and Output Delay constraints

SETUP AND HOLD TIME

Different Timing Terminology (launch/Capture path,Slew, Clock latency,Clock skew)

Setup and Hold Time

Setup and Hold Check and corresponding Equations

Basic Timing Report

ADVANCE TIMING CONCEPTS

Gloabal Setup-hold time

Onchip Variations (OCV),Advance onchip Variation (AOCV),Setup and Hold Check in case of OCV, AOCV

CRP & CRPR

Multi-Mode Multi-Corner timing analysis

TIMING OPTIMIZATION & TIMING CLOSURE METHODS

Pre-placement (After synthesis) optimization

Pre-CTS (during or after placement or floorplaning) optimization

Fixing of Setup and Hold Violation at Logic Synthesis (front-end vlsi)

POST LAYOUT STA (BACKEND) & FIXING SETUP AND HOLD VIOLATIONS METHODS

Post CTS or Pre-Route (After CTS)Optimization

Signoff Timing or Post-Route (After Routing) Timing Closure

Trainer Details:

Puneet Mittal – 17+ Years of Industry Experience & 5+ Years of Entrepreneur Experience. He is the Founder and CEO of VLSI Expert Pvt. Ltd.
LinkedIn Profile - https://www.linkedin.com/in/mittalpuneet