Module 1: Digital Basics (Revision of Engineering course work)
- Binary System, Logic Levels, Different Logic States, Noise Margins
- Combinational circuit (Adder, Subtractor, Mux, Decoder, Encoder)
- Sequential circuit (Flip-flop, Latches, Characteristics tables, Flop conversation, Counters, MOD Counters, Shift Registers)
- Frequency Divider/Multiplier Circuit
- Sequence Detector
- FSM (Mealy and Moore Models)
Module 2: Advance Digital (Implementation of Digital circuit in VLSI design)
- Designing of Different Logic gates / Flip-Flop and Latches using MUX
- 2x1 Mux to 4x1 Mux and which one we prefer and why?
- 2:4 Decoder to 4:16 decoder and which one is preferred and why?
- PAL, PLA concepts
- Tristate Buffers / Tristate Inverter
- Clock Gating Concepts using AND/OR/NAND/NOR Gate and MUX
- Memory concepts and use of decoder and Mux in Memory circuit
- Standard Cell Library Concepts
- Logic Optimization
Module 3: Linux (Basics and Advance)
Section 1: Fundamental
- Development, Architecture and Features of Linux OS
- Bash Scripting
- Basic and Advanced Commands
- Managing File System
- Environment Variables
- File Handling
- Shell Programming.
- Parameter handling and command substitutions.
- Functions – Recursion writing.
Section 2: Advance
- SED (Streaming Editor).
- AWK (pretty printing).
- Regular Expressions
- TCL Scripting
- Make utility (Makefile Writing for different tools and scripts).
- Signals and Traps.
- Cheat sheet.
Module 4: C/C++ Programming
- Understanding of C/C++.
- Constant, Variables and Data Types.
- Operators and Expressions.
- Input and Output Management.
- User Defined Functions.
- Structures and Unions.
- Programming Process and Control Statements.
- C++ Preprocessor, Variable Scope and Functions.
- OOPs (Simple & Advance Classes).
- Pointers.
- Advanced Programming Concepts (File Input/Output, Debugging & Optimization, Operator Overloading, and Floating Point).
Module 5: Verilog HDL
Section 1: Fundamental
- VLSI Design Verification Flow.
- Different Modeling Styles.
- Predefined Gate Primitives.
- Continuous Data Assignments.
- Hierarchy Creation, Module Instantiation and Mapping.
- Stimulus Creation.
- All types of Operators at any level of abstraction.
- Behavioral Modeling.
- Multiway Branching and Generate Blocks.
- Delays, Event Control and Timing Regions at Higher Level of Abstraction.
- Compiler Directives.
- System Tasks and Functions.
- Switch Level Modeling (Lowest Level Abstraction Level).
- User Defined Primitives (UDPs).
- Variable Change Dump (VCD).
- Specify Block.
- Tasks and Functions.
Section 2: Advance
- RTL coding in different modeling styles
- RTL coding for custom IPs
- RTL coding for custom and standard Protocols used in modern SoCs
- Create RTL wrappers to connect 3rd party and custom RTLs
- Understanding of Synthesis in RTL
- Understanding of Linting in RTL
Module 6: System Verilog
Section 1: Fundamental
- Arrays, Structures and Data Types.
- Program Control and Hierarchy.
- Tasks and Functions New Features.
- Interfaces.
- Hierarchy and Connectivity of modules.
- IPC (Inter Process Communication).
- Semaphore and Mailbox.
- Programs & Clocking Block.
- Object Oriented Programming (OOP).
- Randomization.
- Functional Coverage.
- SVA (System Verilog Assertions).
- Verification Environment.
- Labs.
Section 2: Advance
- Design Guidelines using System Verilog
- Object Oriented Verification Testbench Architecture
- Functional Verification
- Functional Coverage metric
- Formal Verification
- Stimulus writing using System Verilog
- Interface wrappers and clocking blocks
- Stimulus for read and write transactions
Module 7: UVM (Universal Verification Methodology)
Section 1: Fundamental
- Introduction to UVM.
- UVM Reporting.
- UVM Transaction.
- UVM Configuration.
- UVM Factory.
- UVM Sequences.
- UVM Transaction Level Modeling (TLM).
- UVM Callback.
- UVM Testbench.
- Testbench Top
- UVM Test
- UVM Environment
- UVM Scoreboard
- UVM Agent
- UVM Monitor
- UVM Driver
- UVM Phases
- UVM Sequencer
Section 2: Advance
- Understanding of Standard UVM Library and Syntax
- Create Standard Verification Environment
- Create Drivers for Standard Protocols
- Create Test Stimulus
- Create Custom Sequences
- Create Checkers
Module 8: Projects
Section 1: Modern SoC On-Chip Protocols
- I2C
- AMBA-APB
- AMBA-AHB
- AMBA-AXI
Section 2: Other Projects
- Synchronous and Asynchronous FIFO
- Dual Port RAM
- RISC Processor
- Traffic Light Controller
NOTE: TEST AND INTERVIEW CAN BE TAKEN AT ANY MOMENT
Q- Who is giving this training?
ANS: This training is being conducted by EICT Academy IIT Guwahati" in collaboration with "VLSI Expert Pvt. Ltd." as Industry Partner
Q:- What is going to me mode of delivery of this training ?
ANS: This is an Instructor Led online Training.
Q: - What if I miss a session?
ANS: No issues if you miss a session the same will be available on our online platform and you can go through is as many time as possible though the instructor won’t be available to solve your queries.
Q: - Is it Certification Course?
ANS: - Yes this is a certification Course.
Q: - Who will give the training Certificate?
ANS: - The training Certificate will be given by " EICT Academy IIT Guwahati"
Q: - Is it a Refundable Course?
ANS: - Yes this is a refundable course the entire amount will be refunded Except the Registration fees Which amount to Rs.5000/-
