"When you know what to do, that's awareness. When you can do it, that's skill." — These programs build both. Hands-on, Synopsys tools-based, guided by VLSI industry professionals.
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RTL to GDSII Workshop
Full digital design flow in 1–5 days. RTL simulation, synthesis, place and route, signoff. Using Synopsys VCS, DC, ICC2, PrimeTime.
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Analog Custom Layout
Schematic to GDSII custom flow. DRC/LVS, layout techniques, matching, symmetry. Synopsys Custom Compiler.
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ASIC Verification
SystemVerilog and UVM basics. VCS simulation, Verdi debug. Testbench creation and functional coverage.
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Static Timing Analysis
STA concepts and hands-on on PrimeTime. Setup/hold, timing reports, constraint writing.
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Faculty Development Programs
FDPs for faculty members — tool upskilling, industry methodology, curriculum design guidance.
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Custom / University Programs
Designed around your institution's requirements. Any duration, any topic. Delivered on your campus.