Curriculum
What You'll Cover
- Delay concepts — cell delay, gate delay, interconnect delay
- Timing paths — startpoints, endpoints, data and clock paths
- Liberty (.lib) file — timing arcs, cell delay models
- Setup and hold timing checks — slack, DRV
- Timing reports — reading and interpreting PrimeTime output
- Clock constraints — create_clock, generated clocks, SDC
- Input/output constraints — set_input_delay, set_output_delay
- Clock tree analysis — skew, latency, jitter effects on timing
- Multi-corner, Multi-mode (MCMM) analysis
- Signal integrity — crosstalk, glitch, SI-aware STA
- ECO — engineering change orders for timing closure
- Timing violations — root cause analysis and fix methods
- Advanced topics — OCV, AOCV, POCV, on-chip variation
- Projects — full STA analysis and timing closure on real design
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